Analog Design, Architect – High‑Speed SerDes

Role Overview

We are seeking a highly experienced Architect specializing in high‑speed SerDes design with deep expertise in advanced analog / mixed‑signal circuits, XSR (Extra‑Short‑Reach) interfaces, and optical I / O technologies. In this role, you will provide technical leadership across complex, next‑generation PHY architectures, driving innovation from concept through production. You will work with cross‑functional teams and influence strategic direction across product lines while solving highly complex design challenges in advanced process nodes.

Key Responsibilities

Advanced SerDes Architecture

• Lead the architectural definition of the E224+ SerDes, including identifying required modifications to meet customer‑driven performance, power, and latency targets.
• Architect and specify high‑performance analog front‑ends, including CTLE / DFE, TX FIR filters, PLLs / CDRs, ADC / DAC‑based architectures, and clocking subsystems.
• Updated channel modeling assumptions
• VSR‑specific equalization strategies
• AFE re‑partitioning and optimization
• Clocking improvements and tighter jitter budgets
• Lead feasibility analysis and modeling of next‑generation SerDes channels, including electrical, XSR, and optical interconnect environments.
• Drive innovation in optical I / O, including modulator / driver integration, TIAs, and photonics‑electrical co‑design workflows.
• Technical problem-solving leading debug of complex silicon issues spanning analog, digital, packaging, and optical domains.
• Develop innovative solutions to challenging PHY‑level problems using deep expertise in circuits, channel modeling, and system behavior.
• Partner with cross‑disciplinary teams to contribute to long‑term technology strategy in SerDes, chiplets, and optical‑interconnect domains that are aligned to industry trends.

Analog & Mixed‑Signal Design

Required Qualifications

Preferred Qualifications

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