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Senior Engineer I - Packaging
Senior Engineer I - PackagingMicrochip Technology Inc. • Burnaby, Metro Vancouver Regional District, CA
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Senior Engineer I - Packaging

Senior Engineer I - Packaging

Microchip Technology Inc. • Burnaby, Metro Vancouver Regional District, CA
1 day ago
Job type
  • Full-time
Job description

Overview

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description

This position for an Intermediate Package Development Engineer who will oversee and manage all aspects of IC package development from initial design and performance considerations, to package design optimization, determining design rules for manufacturing, selecting and interfacing with suitable technology and manufacturing partners and completing package qualification, cooperate with internal business unit designers, operations teams, and reliability resources, and final release products to production. The primary business unit requires packaging in flip chip BGA packaging using Cu Pillar Bump, high-density build-up substrates, multi-chip modules, system-in-package, and other leading-edge advanced packaging solutions.

Responsibilities

  • Work with the designated business units and co-design package solutions that meet the performance, thermal, and reliability requirements for the designated application space.
  • Identify suitable IC package options and perform feasibility studies for all NPI (new product introduction), provide direct interface with multiple third-party assembly sites as well as internal design groups, product engineering, and product marketing and act as the available expert resource for packaging-related aspects of the product.
  • Ensure early success in package development with substantial modeling and simulation for thermal, mechanical and electrical aspects. In addition, act as the thermal and mechanical expert resource for product validation and application teams and end customers for support on system-level solutions.
  • Oversee evaluation and development of new packaging materials and processes.
  • Manage qualifications of new packages or package changes to ensure quality and mitigate risk.
  • Author corporate and supplier-level presentations outlining package roadmaps and package technologies.
  • Author and maintain design rules documents and application notes on package-specific topics.
  • Draft preliminary package outline drawings for internal product development teams.
  • Initiate and follow up on assembly build instructions for all engineering builds.
  • Assist with global cost reduction, standardization and new system implementation projects.

Requirements / Qualifications

  • BSME, BSEE or BS in Chemical Engineering plus 5 years of experience.
  • Experience with advanced laminate (BGA) and QFN package design and assembly.
  • Well-developed knowledge of thermal & electrical simulations, ideally Siemens Flotherm or Ansys Workbench and related tools.
  • Experience with thermal design considerations, including heat sink design and selection.
  • Superior communication and presentation skills and the ability to lead a small team as needed including mentoring junior engineers.
  • Ability to problem-solve and assist the reliability group on FA’s on assembly related failures.
  • Knowledge of JEDEC qualification methods for advanced BGA and high-power ICs.
  • Ability to carry out multiple projects simultaneously, set timelines and prioritize projects.
  • Ability to author and comprehend engineering drawings.
  • Familiarity with ANSI Y-14 drafting nomenclature.
  • Travel to Asia occasionally to attend technology reviews and resolve subcon issues.
  • Competence in working with multiple databases, technical acronyms and complex data sets.
  • Beneficial Skills

  • Package Design using Cadence APD.
  • High frequency / SI analysis knowledge.
  • Travel

    0% - 25%

    Pay Range

    We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below :

    Benefits of working at Microchip

    The annual base salary range for this position is $86,000- $186,000.

    Agency Notice

    To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

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    Senior Engineer I Packaging • Burnaby, Metro Vancouver Regional District, CA

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