Design Verification Engineer
LanceSoft, Inc.Markham, Ontario, Canada7 days ago
Job type
- Full-time
Job descriptionExperience with SystemVerilog, Verilog and C / C++ is a must Strong understanding of the UVM-based verification methodology Experience with Low Power Verification and debug methodology is a must VCS / DVE familiarity is necessary. Ability to juggle multiple on-going tasks at a time. Strong, independent working ability Strong teamwork and communication skills Good attention to detail and creative thinking ability
Pay Rate : $100.00 / hr to $125.00 / hr
Location : Markham, ON Canada
The Role :
The team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced ASIC Design Verification engineer, who will be involved in different aspects of verification activities. The candidate will manage / utilize a variety of verification components to ensure the robustness of RTL designs.
RESPONSIBILITIES :
- Maintaining and enhancing verification environment and regression workflow
- Triaging and debugging regression results
- Analyzing test plan coverage
- Writing, modifying, and maintaining test cases and libraries in SystemVerilog / UVM / Ruby
PERSONAL QUALITIES AND KEY SKILLS
Successful candidate should possess the following personal qualities and technical skills (5+ years) :